Western Digital’s RISC-V "SweRV" Core Design Launched For Free

Western Digital has revealed a design abstraction on register-transfer-plane (RTL) of its self-designed SweRV RISC-V core . The SweRV core is considered one of a number of RISC-V tasks that the corporate has undertaken as a part of its efforts to steer the ISA, its ecosystem, and to advertise its personal transition from licensed, licensed CPU cores. Based on the extra open design targets of RISC-V, the discharge of the high-level illustration of SweTV signifies that third events can use them in their very own chip designs, making not solely the core design but additionally the RISC widespread -V structure normally.

The RTL design abstraction of the Western Digital RISC-V SweRV kernel is now accessible at GitHub . The design is licensed beneath the Apache 2.zero license. This can be a very licensing (and never a copyleft) license that permits the Core for use at no cost, with or with out modifications, with out requiring any modifications. In actual fact, the necessities of the license are fairly low; Along with the necessity for correct affiliation, the one different limitation is that third-party builders can’t use Western Digital's emblems to establish their work.

gif;base64,R0lGODlhAQABAAAAACH5BAEKAAEALAAAAAABAAEAAAICTAEAOw== - Western Digital’s RISC-V "SweRV" Core Design Launched For Free

Western Digital's RISC-V SweRV is a 32-bit in-order core that includes a superscalar 2-way design and a nine-stage pipeline. Applied in a 28nm course of expertise, the core runs at as much as 1.8GHz. Based mostly on Western Digital simulations, the SweRV core delivers four.9 CoreMark / MHz, which is barely larger than the ARM Cortex-A15. The core developer plans to make use of their RISC V cores for their very own embedded designs, equivalent to flash controllers and SSDs, however it’s unclear when these chips ought to be accessible.

gif;base64,R0lGODlhAQABAAAAACH5BAEKAAEALAAAAAABAAEAAAICTAEAOw== - Western Digital’s RISC-V "SweRV" Core Design Launched For Free

As one of many predominant proponents of RISC-V, Western Digital believes that third events will permit using the core to drive the introduction of RISC-V structure by and software program designers. The latter will be sure that Western Digital's personal future designs are higher supported by software program builders.

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Supply: Western Digital / Github

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