In a publicly accessible doc discovered on Twitter by an Eagle-infested consumer, Cisco unveiled some particulars concerning the future Whitley platform and the Barlow Move: the applied sciences Cooper Lake and Ice Lake Xeon Scalable based mostly.
The doc describing the Cisco Unified Computing System was launched to Cisco clients in December 2018 to plan their future improve technique. The doc focuses, as one may anticipate, on the Cisco community portfolio, but in addition exhibits a roadmap on the corporate's present M5 server platform and the upcoming M6 platform.
Cisco declares its M6 server platform for Cooper Lake and Ice Lake as anticipated within the first half of 2020. That is in keeping with our evaluation, though Intel Cooper could also be too gradual on roadmaps already displayed, displaying that Cooper Lake is a 2019 platform (clearly by late 2019).
The Whitley platform will comply with the Purley platform, and this doc confirms that Whitley (which helps Cooper Lake and Ice Lake) may have eight DDR4 channels with as much as DDR4-2933 reminiscence. It will require a brand new socket for the extra channels we all know as LGA4189 and can equate Intel by way of the variety of channels with AMD's EPYC platform.
The doc additionally sheds mild on Intel's PCIe technique. We've already seen that AMD will launch its new Rome processors in 2019 with PCIe four.zero help, and Intel will comply with with Cooper Lake and Ice Lake. Nonetheless, it seems like Intel is breaking apart this technique. On this doc, Cooper Lake is listed as PCIe three.zero / four.zero, which means that there are two completely different variations or that PCIe three.zero is taken into account the beginning date and four.zero later. We're undecided, however Ice Lake is listed from the gate as PCIe four.zero.
It's price noting that the motherboards will help Whitley Cooper Lake and Ice Lake, so that they'll have to supply PCIe four.zero instantly from the gate. If Cooper Lake releases solely elements of PCIe three.zero, motherboards that help PCIe three.zero just for particular clients could seem (much like DDR reminiscence swapping). That is nonetheless unclear at the moment.
It’s price noting that this doc refers to Cooper Lake as Copper Lake. Since that is an official doc, we assume that that is only a typographical error. It additionally doesn’t listing the method applied sciences for Cooper and Ice, though they had been introduced in December. That is most likely only a delay in info dissemination.
Intel Structure Day Cowl Image That includes an Ice Lake Xeon Scalable LGA4189 Processor